Conception d’un processeur DSP faible nergie en logique ternaire

This paper deals with design and performance estimation of typical units blocks of a ternary DSP using SUS-LOC concepts. SUS-LOC enables the design of ternary logic cells and is based upon the use of enhanced and depleted MOS transistors. After the presentation of the basic concepts and of the transistor models required for SUS-LOC specific transistors, we show the design of ternary combinatorial and sequential cells. VHDL is used to obtain performances modelling and architectural-level simulation. A created characterization process allows to extract the delay and the energy consumption information from each cell. Concerning the DSP, we focused on the arithmetic and memory units and studied several binary arithmetic structures like ripple carry adder, CLA and Sklansky adders, . . . in order to extend them to ternary logic. We also show the interest of ternary logic for reducing the power due to the interconnections.